Fixed Width Booth Multiplier using Error Compensation

In many multimedia and digital-signal processing (DSP) applications, multipliers are considered to be the basic arithmetic units. These multipliers significantly influence the system’s performance and power dissipation. To achieve high performance, the modified Booth encoding has been widely adopted in parallel multipliers. It reduces the number of partial products through performing multiplier re-coding. The number of adder cells in the Booth multiplier architecture can be reduced by various techniques. The process of truncation can be done so that the multiplier structure can be simplified to form a fixed width multiplier. The 2n bit product that is to be obtained from the multiplication of n bit multiplicand and n bit multiplier is truncated to n output bits by eliminating the adder cells needed for the addition of n least-significant bits (LSBs). The elimination of certain adder cells can cause truncation error. Hence, appropriate compensation biases are to be introduced into the retained adder cells. The compensation circuit needed for reducing truncation error is also designed here. Our proposed encoder was simulated in Mentor Graphics Model Sim 10.1c, using Verilog HDL. The output of the encoder was synthesized using Leonardo Spectrum. The synthesis results show that the critical path delay as well as the total number of gates is reduced when compared with the prevailing technology.